1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to the art of erasing microelectronic flash Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method of erasing a microelectronic flash Electrically Erasable Programmable Read-Only Memory device that tightens the V.sub.T distribution.
2. Discussion of the Related Art
One type of programmable memory cell is commonly referred to as a flash memory cell. The structure of one type of flash memory cell includes a source and a drain formed in a silicon substrate. The structure of another type of flash memory cell includes a source and a drain formed in a well that is formed in a silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of a flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer.
Programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such a programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain.
Such a relatively high voltage potential applied between the drain and source causes electrons to flow through the channel region from the source to the drain. The electrons flowing between the source and drain can attain relatively high kinetic energy levels near the drain. In addition, the high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate usually attracts the electrons flowing through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of a flash memory cell to cause conduction through the channel region during a read operation on the flash memory cell. The time involved in a programming operation depends upon the rate at which electrons are injected onto the floating gate. As can be appreciated, the slower the rate of injection the longer the programming time to reach the desired threshold voltage.
With such programming techniques, the relatively high voltage potential of the floating gate at the start of the programming operation is reduced as electrons accumulate on the floating gate. Such a reduction in the voltage potential of the floating gate causes a corresponding reduction in the rate of electron injection onto the floating gate. Such a reduction in the rate of electron injection increases the time required to program a flash memory cell to the desired threshold voltage. Such increased programming time slows the overall speed of flash memory devices that employ such programming techniques.
In addition, it is well known that a hot carrier programming technique results in the formation of electron-hole pairs in the channel region of the flash memory cell near the drain. The electron-hole pairs are formed when high-energy electrons bombard the crystal lattice structure of the silicon substrate and dislodge other electrons from the lattice. Moreover, the portions of the channel region near the drain usually have a relatively high voltage potential due to the high voltage applied to the drain. As a consequence, the voltage potential of the floating gate can fall below the voltage potential of the portion of the channel region located near the drain as the voltage level on the floating gate decreases during programming. Under this condition, holes from the electron-hole pairs that are created in the channel region near the drain can migrate throughout the tunnel oxide layer and onto the floating gate. Such migration of holes onto the floating gate causes surface damage to the tunnel oxide layer. Such surface damage usually causes long-term reliability problems in the flash memory cell by reducing the rate of injection of electrons onto the floating gate during programming. In addition, such surface damage can interfere with current flow through the channel region of the flash memory cell during a read operation that also results in a reduction in long-term reliability.
The microelectronic flash or block-erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that would enable the cells to be erased independently. As a result, all of the cells must be erased together as a block.
A flash memory device of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor (FET) memory cells. Each of the FETs includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, to read the cells, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying programming voltages as follows: a voltage, typically in the range of 9-10 volts to the control gate, a voltage of approximately 5 volts to the drain and grounding the source. As discussed above, these voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein that increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying a voltage of about 5 volts to the control gate, applying about 1 volt to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. Another method of erasing a cell is by applying 5 volts to the P-well and minus 10 volts to the control gate while allowing the source and drain to float.
A problem with conventional flash EEPROM cells is that because of manufacturing tolerances, some cells become over-erased before other cells become sufficiently erased. The floating gates of the over-erased cells are either completely or partially depleted of electrons and have a very low negative charge or become positively charged. The over-erased cells can function as depletion mode transistors that cannot be turned off by normal operating voltages applied to their control gates and introduce leakage current to the bit line during subsequent program and read operations. The slightly overerased cells can introduce varying amounts of leakage current to the bitline depending upon the extent of overerasure.
More specifically, during program and read operations only one wordline is held high at a time, while the other wordlines are grounded. However, because a positive voltage is applied to the drains of all of the cells and if the threshold voltage of an unselected cell is very low, zero or negative, a leakage current will flow through the source, channel and drain of the cell.
The undesirable effect of leakage current is illustrated in FIG. 4, which is a simplified electrical schematic diagram of a column 400 of flash EEPROM cells 402, 404, 406, and 408. The sources of the column 400 of transistors are all connected to a source supply voltage V.sub.S. A programming voltage V.sub.CG is applied to the control gate of the transistor 404, which turns it on. A current I.sub.2 flows through the transistor 404 from ground through its source, channel (not shown) and drain. Ideally, the bitline current I.sub.BL is equal to I.sub.2. However, if one or more of the unselected transistors, for example transistors 402, 406 or 408 as illustrated in FIG. 4, are overerased or slightly overerased, their threshold voltages will be very low, zero or even negative, and background leakage currents I.sub.1, I.sub.3, and I.sub.4 could flow through the transistors 402, 406, and 408, respectively. The bitline current I.sub.BL would then be equal to the sum of I.sub.2 and the background leakage currents I.sub.1, I.sub.3 and I.sub.4. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistor cells are connected to each bitline. If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of any cell on the bitline and therefore renders the memory inoperative.
It is known in the art to reduce the threshold voltage distribution by performing an over-erase correction operation, which reprograms the most over-erased cells to a higher threshold voltage. An over-erase correction operation of this type is generally known as Automatic Programming Disturb (APD).
A preferred APD method which is referred to as Automatic Programming Disturb Erase (APDE) is disclosed in U.S. Pat. No. 5,642,311, entitled "OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS," issued Jun. 24, 1997 to Lee Cleveland. This patent is assigned to the same assignee as the present invention and is incorporated herein by reference in its entirety. The method includes sensing for over-erased cells and applying programming pulses thereto, which bring their threshold voltages back up to acceptable values.
Following application of an erase pulse, under-erase correction is first performed on a cell-by-cell basis by rows. The cell in the first row and column position is addressed and erase verified by applying 4 volts to the control gate (wordline), 1 volt to the drain (bitline), grounding the source, and using sense amplifiers to sense the bitline current and thereby determine if the threshold voltage of the cell is above a value of, for example, 2 volts. If the cell is under-erased, indicated by a threshold voltage above 2 volts, the bitline current will be low. In this case, an erase pulse is applied to all of the cells, and the first cell is erase verified again.
After application of each erase pulse and prior to a subsequent erase verify operation, over-erase correction is performed on all of the cells of the memory. Overerase verify is performed on the bitlines of the array in sequence. This is accomplished by grounding the wordlines, applying typically 1 volt to the first bitline, and sensing the bitline current. If the current is above a predetermined value, this indicates that at least one of the cells connected to the bitline is over-erased and is drawing leakage current. In this case, an over-erase correction pulse is applied to the bitline. This is accomplished by applying approximately 5 volts to the bitline for a predetermined length of time such as 100 .mu.s.
After application of the over-erase correction pulse the bitline is verified again. If bitline current is still high indicating that an over-erased cell still remains connected to the bitline, another over-erase correction pulse is applied. This procedure is repeated for all of the bitlines in sequence.
The procedure is repeated, as many times as necessary until the bitline current is reduced to the predetermined value, which is lower than the read current. Then, the procedure is performed for the rest of the cells in the first row and following rows until all of the cells in the memory have been erase verified.
By performing the over-erase correction procedure after each erase pulse, the extent to which cells are over-erased is reduced, improving the endurance of cells. Further, because over-erased cells are corrected after each erase pulse, bitline leakage current is reduced during erase verify, thus preventing under-erased cells from existing upon completion of the erase verify procedure.
FIG. 5A illustrates how the threshold voltages of the cells or bits in a flash EEPROM can differ following an erase operation as shown by curve 500 that represents the number of cells having particular values of threshold voltage V.sub.T. It will be seen that the least erased cells will have relatively high threshold voltages in the region of V.sub.T MAX, whereas the most overerased cells will have low threshold voltages in the region of V.sub.T MIN that can be zero or negative. The characteristic curve illustrated in FIG. 5 is known as the threshold voltage distribution. The dashed portion of the curve 502 show the threshold voltages of the cells in a flash EEPROM after the overerase correction operation. It is noted that correcting the V.sub.T of the most overerased cells has changed the threshold voltage distribution. However, the threshold voltage distribution curve 502 indicates that there is a number of cells that still have a very low threshold voltage.
Because the background leakage current of a cell varies as a function of threshold voltage, the lower (more negative) the threshold voltage the higher the leakage current. Because there may be as many as 512 cells connected to a bitline, the background leakage current may still be sufficient to exceed the cell read current. It is therefore desirable to prevent cells from not only being over-erased but to reduce the threshold voltage distribution to as low a range as possible, with ideally all cells having the same high threshold voltage after erase on the order of 2 volts.
Therefore, what is needed is a method to tighten the threshold voltage distribution to as low a range as possible by increasing the threshold voltage of the cells with the lowest threshold voltage without affecting the threshold voltage of the cells with the highest threshold voltage.